1. Field of the Invention
The present invention relates to a high speed serial buffer. More specifically, the present invention relates to a method and structure for improving system performance of a high speed serial buffer.
2. Related Art
Conventional serial buffers implement one or more serial ports using an advanced interface protocol, such as the serialized rapid input/output (sRIO) protocol, or a Lite-weight protocol, such as SerialLite (as specified by FPGA maker Altera) or Aurora (as specified by FPGA maker Xilinx).
Conventional serial buffers include various on-chip resources, such as a buffer memory, configuration registers and flag/error registers. The buffer memory typically facilitates data transfer through the serial buffer, while the configuration registers and flag/error registers typically control the operation of the serial buffer. Different types of incoming packets are provided to the serial port of the serial buffer to access these different on-chip resources. A conventional serial buffer includes a single buffer for receiving and storing all of these different types of packets. However, some types of packets may require longer processing times than other types of packets within the serial buffer. For example, a relatively long processing time may be associated with a packet that requests read data from the buffer memory of the serial buffer, while a relatively short processing time may be associated with a packet that accesses a configuration register of the serial buffer. It is possible for packets having relatively long associated processing times to block subsequently received packets having relatively short associated processing times. In this case, the serial buffer must wait until the packets having relatively long processing times have been processed before processing the packets having relatively short processing times. System performance of the serial buffer is degraded when such a blocking condition is encountered.
It would therefore be desirable to have a serial buffer that eliminates the above-described blocking conditions.